1. Field of the Invention
The present invention relates to a pipeline controlling system for a calculator, and particularly to a pipeline controlling system which is capable of improving processing speed.
2. Description of the Prior Art
A pipeline controlling system has been adopted in a recent microprocessor to improve the processing speed thereof. The pipeline controlling system divides an instruction into several stages and processes it such that the respective stages are operated parallel to each other, and such that an instruction to be processed next is read before completing the processing of the first instruction.
FIG. 1 is a block diagram showing the constitution of a conventional pipeline controlling system which comprises a first instruction register 1, a second instruction register 3, a register file 5, a comparator 7, and an effective address calculating portion 9. In FIG. 1, the first instruction register 1 stores and holds a preceding instruction which is in an execute phase. The second instruction register 3 stores and holds a succeeding instruction to be executed after the preceding instruction. The instruction stored in the second instruction register 3 is subjected to the calculation of an effective address thereof.
The register file 5 has a plurality of registers such as base registers and index registers to be used for executing the preceding instruction stored in the first instruction register 1 and calculating the effective address of the succeeding instruction stored in the second instruction register 3. In the register file 5 a register used for executing the preceding instruction is selected in accordance with the information of a Reg1 field of the preceding instruction stored in the first instruction register 1, namely, in accordance with the value of a DR field which indicates the register to be used by the first instruction register 1 in executing the preceding instruction. A register used for calculating the effective address of the succeeding instruction is selected in the register file 5 in accordance with the information of a Reg2 field of the succeeding instruction stored in the second instruction register 3, namely, in accordance with the value of an IX field which indicates the register to be used by the second instruction register 3 in calculating the effective address.
The comparator 7 is arranged to compare the information of the Reg1 field of the preceding instruction stored in the first instruction register 1 with the information of the Reg2 field of the succeeding instruction stored in the second instruction register 3. As a result of the comparison, if the information of the Reg1 field coincides with the information of the Reg2 field, i.e., if the register to be used in executing the preceding instruction is the same as the one to be used in calculating the effective address of the succeeding instruction, the comparator 7 outputs a coincidence signal to the effective address calculating portion 9.
On the other hand, if the information of the Reg1 field does not coincide with the information of the Reg2 field, i.e., if the register used for executing the preceding instruction differs from the one used for calculating the effective address of the succeeding instruction, the comparator 7 outputs a noncoincidence signal to the effective address calculating portion 9.
The effective address calculating portion 9 is constructed to calculate the effective address of the succeeding instruction stored in the second instruction register 3. Namely when the noncoincidence signal is supplied from the comparator 7 to the effective address calculating portion 9, the effective address of the succeeding instruction is calculated by using the register of the register file 5 which has been selected in accordance with the information of the Reg2 field of the succeeding instruction stored in the second instruction register 3, and, in parallel with this calculation, the preceding instruction is executed and processed by using the register with the information of the Reg1 field of the preceding instruction.
On the other hand, if the register used for executing the preceding instruction coincides with the register to be used for calculating the effective address of the succeeding instruction and, therefore, if the comparator 7 outputs a coincidence signal to the effective address calculating portion 9, the execution of the preceding instruction is completed first as shown in FIG. 2 to define information to be stored in the register which has been used for executing the preceding instruction. After that, the effective address of the succeeding instruction is calculated according to the defined information.
As described in the above, when a register to be used for executing a preceding instruction stored in the first instruction register 1 coincides with a register to be used for calculating the effective address of a succeeding instruction stored in the second instruction register 3, the conventional system executes the preceding instruction first to define the contents of the register used for executing the preceding instruction, and then calculates an effective address of the succeeding instruction.
Depending on the kind of preceding instruction stored in the first instruction register 1, there may be a case that, after the execution of the preceding instruction, the contents of a register designated by the Reg1 field of the preceding instruction and used for executing the instruction remain the same before and after the execution. In this case, if an effective address of the succeeding instruction is calculated after the completion of the execution of the preceding instruction as described in the above, the calculation of the effective address is delayed. Therefore, the speed of the pipeline processing is lowered, thereby decreasing the processing speed of a calculater which executes pipeline processing.